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APPENDICES 4.A.1 Relationship Between Impedance and Turn Ratio of Transformer Baluns with Two Stacked Transformers There are four ways to build a transformer balun by two stacked transformers with any turn ratio of 1: n. a) SS-DS connection mode: Single-ended, primary windings stacked in Series, goes to Differential, secondary windings stacked in Series. b) SP-DS connection mode: Single-ended, primary windings stacked in Parallel, goes to Differential, secondary windings stacked in Series. c) DS-SS connection mode: Differential, primary windings stacked in Series, goes to Single-ended, secondary windings stacked in Series. d) DS-SP connection mode: Differential, primary windings stacked in Series, goes to Single-ended, secondary windings stacked in Parallel. Figure 4.A.1 shows four ways to build a transformer balun by two stacked transformers with their turn ratio, 1 : n. The 1 G resistor is a dummy part to satisfy the requirement for a DC circuit-loop in either transformer 1 or transformer 2.

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SOI MOSFETs are free of some of the efffects that tend to reduce the performance of their bulk counterparts. In particular they present reduced junction capacitances, a very small body factor, and, hence, a near-.ideal subthreshold slope and high current drive. These different properties are detai led next. 5.3.1 Source and Drain Capacitance In bulk MOS devices, the parasitic ctrain (or source)-to-substrate (or well) capacitance consists of two components,: the capacitance between the junction and the substrate itself and the capacitaace between the junction and the channelstop implant under the field oxide. As devices are shrunk to smaller geometries, higher substrate doping concentrations are used and the junction capacitance increases. In SOI devices with reach-through junctions, the junction capacitance has only one component: the capacitance of the MOS structure made of the junction (gate electrode of the MOS structure), the buried oxide (gate oxide of the MOS structure), and the underlying silicon substrate (substrate of the MOS structure). This parasitic capacitance can only be smaller than the capacitance of the buried oxide, which is typically lower than the capacitance junction of a bulk MOSFET by an order of magnitude. This difference further increases as the supply voltage is reduced (Fig. 5.4).29 5.3.2 Fully Depleted, Partially Depleted, and Accumulation-Mode MOSFETs All SOI MOSFETs are not alike. Their physics is highly dependent on the thickness of the silicon film on which they are made. Three types of devices can be

(8.2)

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Fig. 6.4 Fortunately, Greek crosses tessellate the plane (Fig. 6.4), so that many of these chains of bricks will indeed fill space without gaps. John Edson Sweet was an engineer who (like many engineers) had a very good three-dimensional imagination. He was shown a diagram like that in Fig. 6.5, which shows the three pairs of external tangents of three circles of different sizes. It appears that the three points where the tangents meet, A, Band C, lie on a straight line. Sweet's reaction was, 'Yes, that is perfectly self-evident.' He then explained that he visualized the figure as showing three spheres lying on a flat surface. The pairs of tangents were circular cones which touched the spheres in pairs. As well as the table top that they are resting on, there is another plane which can be laid across the spheres, to touch all of them, and the cones. The vertices of the cones must lie on the line in which these two planes meet, so they, of course, lie in a straight line. This visual argument, which is similar to Fig. 6.5

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